BÜCHER VERSANDKOSTENFREI INNERHALB DEUTSCHLANDS
SystemVerilog for Design and Verification using UVM
From RTL to Synthesis
1st ed. 2015
Springer Verlag
ISBN 978-1-4614-1757-6
Standardpreis
Bibliografische Daten
Buch. Hardcover
1st ed. 2015. 2015
100 s/w-Abbildungen, Bibliographien.
In englischer Sprache
Umfang: 300 S.
Format (B x L): 15,5 x 23,5 cm
Verlag: Springer Verlag
ISBN: 978-1-4614-1757-6
Produktbeschreibung
This book is an “A-Z” guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC). To complete this book’s package as a practical guide, readers are introduced to the fundamentals of static timing analysis.
Autorinnen und Autoren
Kundeninformationen
Provides a practical guide to the use of SystemVerilog for both design and verification, unlike any other book currently availableUses the Universal Verification Methodology (UVM) to build test-benches, in a manner accessible to novicesCovers the practical essentials needed for design, verification, synthesis and static timing analysis, which readers might otherwise have to find in several books
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